1. Field of the Invention
The present invention relates to the field of digital computer systems, and more particularly, to power management in a system having a direct memory access controller.
2. Description of Related Art
In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen (16) megabytes of memory. The wide acceptance of the ISA bus has resulted in a very large percentage of devices being designed for use on the ISA bus. However, higher-speed input/output devices commonly used in computer systems require faster buses. A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus machines remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining acceptance in the industry is the peripheral component interconnect (PCI) bus. The PCI bus can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example. Other devices such as graphic display adapters, disk controllers, etc. can also attach directly or indirectly (e.g., through a host bridge) to the PCI bus.
A bridge chip is provided between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip essentially translates the ISA bus cycles to PCI bus cycles, and vice versa.
In a digital computer, a microprocessor operates on data stored in a main memory. Since there are practical size limitations on the main memory, bulk memory storage devices are provided in addition to and separately from the main memory. When the microprocessor wants to make use of data stored in bulk storage, for example, a hard disk, the data is moved from the hard disk into the main memory. This movement of blocks of memory inside the computer is a very time consuming process and would severely hamper the performance of the computer system if the microprocessor were to control the memory transfers itself.
In order to relieve the microprocessor from the chore of controlling the movement of blocks of memory inside the computer, a direct memory access (DMA) controller is normally used. The DMA controller receives information from the microprocessor as to the base location from where bytes are to be moved, the address to where these bytes should go, and the number of bytes to move. Once it has been programmed by the microprocessor, the DMA controller oversees the transfer of the memory data within the computer system. Normally, DMA operations are used to move data between input/output (I/O) devices and memory.
Many computer systems now use some type of "power management" to temporarily place the computer system into a suspend mode in which power is conserved. For example, if the computer system is a laptop computer, a power management device may cause a computer system to enter the suspend mode to save power whenever the laptop is closed. The suspend mode may also be entered if a key on the keyboard has not been pressed for a prolonged period of time. There are numerous other events which will cause a power management device to place the computer system into a suspend mode, and there are numerous available power management devices.
After some period of time, or a defined event occurs (such as the opening of the laptop cover), the power management device enters a resume mode. In the resume mode, the power management device essentially restores the computer system to the state it was in before it entered the suspend mode. This requires that certain information be stored before the computer system enters the suspend mode. One type of information that needs to be stored and available for the resume mode is the addresses contained in address registers of the DMA controller. In particular, the base addresses, indicating the starting address for a destination of transfer data, need to be stored so that the power management software will know where an original DMA transfer address was prior to entering the suspend mode.
In prior power management arrangements, "shadow registers" were used to store the DMA address (the initial base address) when the base address register and the current address register in the DMA controller are written with the base address. (When the current address register is written, the base address register is written simultaneously.) In other words, the power management device will take a write cycle off the PCI bus, although not claiming it as its own, and place the DMA address (the base address) into its shadow register. These shadow registers are needed since the base registers in conventional DMA controllers are not readable, and the power management device would otherwise have no way of knowing what the base address was prior to entering the suspend mode.
This problem is even greater when the computer system is equipped with a scatter/gather programmer that programs the DMA controller with the base address, since the scatter/gather programmer is closely coupled to the DMA controller. This close coupling means that during programming of the DMA controller, the base address does not appear on a bus from which the power management device could see the write cycle and write the base address into a shadow register.
A major disadvantage to using shadow registers is the amount of circuitry and logic that these shadow registers add to the design. A shadow register is needed for each base register in a DMA controller. In a conventional DMA controller for 16-bit operation there are fourteen base registers. If this is extended to 32-bit operation, a DMA controller may have twenty-eight base registers. Power management requires a separate shadow register for each of these twenty-eight base registers.